Logic Gate Simulation Tools

[dr_jaymahdi]

Hi everyone:

I am wondering if there is a good logic gate simulator available in Ubuntu / Linux?

Ideally, I would like the tool to read in a circuit net list full of gates (written in Verilog or VHDL), and simulate a set of test patterns. Is there such a tool out there or is this only available in closed source?

Thanks in advanced for those who respond

[Victicom]

Well... I dont know about the reading the circuit net from VHDL, but maybe this can help you...:

http://ozark.hendrix.edu/~burch/logisim/download.html